1. Field of the Invention
This invention relates generally to memory devices and, more specifically, to a memory device having a switchable clock output pin which will allow for board identification in systems having a plurality of circuit boards.
2. Description of the Prior Art
Presently the standard I.sup.2 C serial Electrical Erasable Programmable Read Only Memory (EEPROM) device has data and clock inputs. The EEPROM device is designed to have the clock and data signals bussed to each EEPROM device in parallel. Addressing of each individual EEPROM device is accomplished by three address pins which couple each EEPROM device to the computer system. The problem with this approach is that the three address pins limit the total number of EEPROM devices that may be coupled to the clock and data lines to eight. A further problem with I.sup.2 C devices being used for board identification for electronic circuit boards is the requirement for the three address pins to be routed to the electronic circuit board connector. This requirement consumes extra connector pins which could be used for different and more important functions.
Therefore, a need existed to provide an improved electronic circuit board and method therefor. The addressing of the improved electronic circuit board must not require the three address pins which are currently being used. This will allow more electronic circuit boards to be placed on the clock and data bus lines. The removal of the requirement of the three address pins will also free up extra connector pins which may be used for different and more important functions. A need further existed to provide an improved method for board identification in systems which use a plurality of electronic circuit boards. The new method must increase the total number of electronic circuit boards which may be placed on the clock and data signal lines.